Building FPGA 18.1¶

• Table of contents
• Building FPGA 18.1
  • Overview
  • Introduction
    • Repository
    • Checking out the repo
    • Repository Structure
  • Development Kit Pre-built Outputs
  • Quick steps to Build
  • Updating the Pinout
  • Opening Platform Designer and Quartus

Overview¶

The provided FPGA images are given as a reference to how the FPGA can be used in unison with the HPS. The FPGA design heavily uses Qsys for connecting functional blocks together and contains the following Qsys blocks:

• sysid_qsys - System ID Peripheral - This basic block stores a 32 Bit system ID and the date the FPGA was built that can be read from the HPS.
• hsmc_out_0 - PIO - This is a parallel I/O block that is connected to part of the full HSMC Connector.
• hsmc_out_1 - PIO - This is a parallel I/O block that is connected to part of the full HSMC Connector.
• hsmc_in_0 - PIO - This is a parallel I/O block that is connected to part of the full HSMC Connector.
• hsmc_in_1 - PIO - This is a parallel I/O block that is connected to part of the full HSMC Connector.
• fpga_ddr - DDR3 SDRAM Controller with UniPHY - This is the DDR controller for the DDR RAM that is attached to the FPGA, in the example it is then routed to the HPS so the HPS can access it from the HPS-to-FPGA AXI Bridge.
• clk_100Mhz - Clock Source - Allows for inputting the CLK2DDR signal into the Qsys.
• mm_clock_crossing_bridge - Avalon-MM Clock Crossing Bridge - Lets the HPS-to-FPGA bridge, running at 100Mhz, talk to the FPGA DDR Controller, running at 150Mhz.

The project also uses the Altera Source and Probe block for controlling signals on the partial HSMC connector for debug purposes. More information can be found at http://www.altera.com/literature/hb/qts/qts_qii53021.pdf.

Introduction¶

The reference project to the MitySOM-5CSx Development Kit utilizes GNU make for building the FPGA from the command line. Please note that the project can be built using the normal flow of Quartus/Platform Designer if that is desired.

These instructions have been tested with Quartus Prime 18.1
Tested host machine: Ubuntu 18.04 and Windows 10

Repository¶

Description	Repository	Branch	Web Viewer
Quartus Reference Project	https://support.criticallink.com/git/mitysom-5csx-ref.git	18.1-stable	gitweb

Checking out the repo¶

The reference projects are on Critical Link's git server, run the following command to clone the repo:

git clone https://support.criticallink.com/git/mitysom-5csx-ref.git -b 18.1-stable

Repository Structure¶

.
├── dev_5cse_h4_3ya [MitySOM 5CSE-H4-3YA Reference Project]
├── dev_5cse_h4_8ya [MitySOM 5CSE-H4-83YA Reference Project]
├── dev_5cse_l2_3y8 [MitySOM 5CSE-L2-3Y8 Reference Project]
├── dev_5csx_h5_4ya [MitySOM 5CSX-H5-4YA Reference Project]
├── dev_5csx_h6_42a [MitySOM 5CSX-H6-42A Reference Project]
├── dev_5csx_h6_4ya [MitySOM 5CSX-H6-4YA Reference Project]
├── dev_5csx_h6_53b [MitySOM 5CSX-H6-53B Reference Project]
└── README.md

Development Kit Pre-built Outputs¶

Models	SD Card Image	FPGA/Bootloaders Binaries
5CSE-H4-3YA	5CSE-H4-3YA SD Card	5CSE-H4-3YA Binaries
5CSE-H4-8YA	5CSE-H4-8YA SD Card	5CSE-H4-8YA Binaries
5CSE-L2-3Y8	5CSE-L2-3Y8 SD Card	5CSE-L2-3Y8 Binaries
5CSX-H5-4YA	5CSX-H5-4YA SD Card	5CSX-H5-4YA Binaries
5CSX-H6-42A	5CSX-H6-42A SD Card	5CSX-H6-42A Binaries
5CSX-H6-4YA	5CSX-H6-4YA SD Card	5CSX-H6-4YA Binaries
5CSX-H6-53B	5CSX-H6-53B SD Card	5CSX-H6-53B Binaries

Quick steps to Build¶

1. Launch the Intel Embedded Command Shell.
   Linux
   

   /opt/intelFPGA/18.1/embedded/embedded_command_shell.sh
   

   
   Windows
   

   Press start button and enter SoC EDS 18.1 Command Shell
   

2. Change into the directory where project was cloned into (Example: /home/user/mitysom-5csx)
   

   cd /home/user/mitysom-5csx

3. Run the following command that will do the following: 1. Generate the qsys, 2. Compile the FPGA, 3. Convert the SOF to an RBF
   

   make rbf

Updating the Pinout¶

Opening Platform Designer and Quartus¶

The Makefile can also be used open Quartus or Platform designer.

Opening Quartus:

1. Open a terminal
2. Enter the following command that will allow you to use the quartus tools from the command line:
   

   /opt/intelFPGA/18.0/embedded/embedded_command_shell.sh

3. Open the current project with Quartus with the Makefile
   

    make quartus_edit

Opening Platform Designer:

1. Open a terminal
2. Enter the following command that will allow you to use the quartus tools from the command line:
   

   /opt/intelFPGA/18.1/embedded/embedded_command_shell.sh

3. Open the current project's top level qsys with Platform Designer with the Makefile
   

    make qsys_edit