Hardware FAQs¶

• Table of contents
• Hardware FAQs
  • In order to route to a PLL does the clock input need to come in on a clock in pin?
  • Why are some FPGA IO pins labeled with a /GND as a valid connection?
    • I.E. pin 58 (labeled as B4A_TX_B77_N/DQ8D/DQ2B/GND)? Is it about compatibility with others FPGA densities? How do I properly use these pins?
  • Occasionally a module fails to boot from the MMC/SD card what could cause this?
  • What is the current HPS DDR3 clock speed?

In order to route to a PLL does the clock input need to come in on a clock in pin?¶

Yes, a PLL can only be sourced from a clock pin. It should be noted than logic can feed a global clock tree but this signal can not feed a PLL.

Why are some FPGA IO pins labeled with a /GND as a valid connection?¶

I.E. pin 58 (labeled as B4A_TX_B77_N/DQ8D/DQ2B/GND)? Is it about compatibility with others FPGA densities? How do I properly use these pins?¶

Pins such as 58 can be used by the HMC (Hard Memory Controller) for DDR3 or LPDDR2 memories on a custom carrier board. All MitySOM-5CSx modules will support this I/O pin and others like it. If you plan on attaching a Hard Memory controlled device to the module this pin would be connected to ground. For all other cases it can be used as an IO. The module itself will not connect this PIN to GND regardless of the density/device type. you can reference Alteras documentation about the hard memory controller for further specific details.

Occasionally a module fails to boot from the MMC/SD card what could cause this?¶

As of October 13, 2014 Altera updated their "Cyclone V Family Pin Connection Guidelines" to include ~10k pull-up resistors on both the SDMMC_CMD and SDMMC_D0 signals. This document - PCG-01014.pdf - is attached (Page 35 in particular). Any recent critical Link MitySOM-5CSx development kits include this change and you should ensure that it has been added to any custom carrier boards.

What is the current HPS DDR3 clock speed?¶

The MitySOM-5CSx family adheres to Alteras Cyclone V maximum memory speeds. At this time we have the HPS memory clocked at 400Mhz as the maximum. A slower speed may be selected if desired down to 300MHz. This may change if Altera makes changes to their Silicon/recommendations.