Reset GPIOs¶

The default UBoot environment from Critical Link toggles the state of 3 GPIO signals, 2 are on module for the USB Phy and are required for proper USB function while the other is for the Ethernet Phy reset signal when using the MitySOM-5CSx Development Board (80-000578). The Ethernet Phy reset signal may change when a custom carrier board is designed and as such may need to change in that situation.

Ethernet Phy Reset GPIO¶

For proper latching of the KSZ9031 Ethernet phy boot mode pins we toggle (clear '0' then set '1') the Ehternet Phy rest signal from within UBoot. A 1 second sleep is added to ensure that the phy has properly come out of reset before its use is attempted.

In this case we are using module pin 253 for the Phy reset (GPIO28).

UBoot Environment Variable to Clear and Set Phy Reset GPIO¶

initphy=gpio c 28; gpio s 28; sleep 1

USB Phy Reset GPIO's¶

HPS GPIO0 is tied to the "USB1_ULPI_CS" signal of the USB Phy on the module; it must be driven high (set '1') to enable the Phy as it has a weak, 10k, pull-down.

HPS GPIO9 is tied to the "USB1_ULPI_RESET_N" signal of the USB Phy on the module; it must be toggled (clear '0' then set '1') after the Chip select it driven high.

setup_usb=gpio set 0; gpio clear 9; gpio set 9

UBoot messages¶

The following messages should be seen when using a default Critical Link MitySOM-5CSx UBoot environment.

gpio: pin 28 (bank/mask = 0/0x10000000)
gpio: pin 28 (gpio 28) value is 0
gpio: pin 28 (bank/mask = 0/0x10000000)
gpio: pin 28 (gpio 28) value is 1
gpio: pin 0 (bank/mask = 0/0x00000001)
gpio: pin 0 (gpio 0) value is 1
gpio: pin 9 (bank/mask = 0/0x00000200)
gpio: pin 9 (gpio 9) value is 0
gpio: pin 9 (bank/mask = 0/0x00000200)
gpio: pin 9 (gpio 9) value is 1