Activity
From 07/07/2016 to 08/05/2016
08/05/2016
- DV 02:05 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board
- Hi Jared,
Sorry for the delay.
I just pushed a dizzy(1.7) branch to our git repo: http://support.criticallink.com/gitweb/?p=meta-mitysom-5csx.git;a=shortlog;h=refs/heads/dizzy
This will use gcc 4.9.1 for the toolchain, which shoul...
08/03/2016
- JK 03:27 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board
- Hello Dan,
I proceeded to try to use Yocto to build the Altera 4.1.22 LTSI RT kernel based on your suggestions above.
Unfortunately, the compilation of the kernel is erroring out because of an incompatible GCC version. The followin...
08/02/2016
- DV 11:55 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board
- Hello Jared,
That sounds like a perfect approach. For building the file system we do use yocto, which as you saw is pointed to use the 3.16 kernel. Now depending on how manual you want to do this I can suggest a few options.
Probab... - JK 10:26 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board
- Hello Dan,
I've been going through the instructions on the Wiki to get an SD card image of my creation working. I'm starting with the 3.16 kernel version provided by Critical Link to get a handle on the process of building an SD card ...
07/29/2016
- DV 03:01 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Using PREEMPT_RT on MitySOM 5CSX Dev Board
- Hello Jared,
I did a quick test here and was able to boot altera's 4.1.22 ltsi rt kernel using the MitySOM-5CSX dev kit. I used the socfpga_defconfig and socfpga_cyclone5_sockit.dts. I didn't do an extensive test but was able to boot ...
07/28/2016
- Context: My company recently purchased some MitySOM 5CSX Development Boards and would like to use them on a current project. This project likely has the need for a real-time operating system. I want to start by using Linux with the PREEM...
07/27/2016
- JC 05:19 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: Communication EGD or ModBus/TCP Cores
- Good question, I'm not sure if there are any files on there that specify which version it is. But if nobody has updated it since you bought it then it will be running the older MDK filesystem.
- HB 05:06 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: Communication EGD or ModBus/TCP Cores
- How can I check my currently devkit MDK?
- JC 03:56 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: Communication EGD or ModBus/TCP Cores
- Looks like you are using the older toolchain which apparently doesn't have the rpl_* support. This post gives some possible solutions.
https://www.linuxquestions.org/questions/linux-software-2/undefined-reference-to-%60rpl_malloc'-5872... - HB 03:34 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: Communication EGD or ModBus/TCP Cores
- Jonathan,
I used the tarball instead of the git, I share you my log, it is different than yours, it is attached.
I can see some Errors. After this Should I be able to compile in Eclipse using the library ?
Thanks,
Hector - JC 01:43 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: Communication EGD or ModBus/TCP Cores
- I created a FAQ entry for future reference to building autotools based libraries.
https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/ARM_Software_FAQs#Building-library-which-uses-autotools - JC 01:33 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: Communication EGD or ModBus/TCP Cores
- Hector Bojorquez wrote:
> I got the error in Eclipse Console messages I have not tried on the MitySOM, I tried the $file command and it looks good
> ...
This shows that the object file your trying to use was built of an intel processo... - HB 11:58 AM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: Communication EGD or ModBus/TCP Cores
- I got the error in Eclipse Console messages I have not tried on the MitySOM, I tried the $file command and it looks good
!File_Command.PNG!
I want to share you the Library installation log, it is attached, the installation created s... - JC 11:03 AM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: Communication EGD or ModBus/TCP Cores
- Where did you get this error? When running the program on the L138?
The error usually indicates the object was built for a different architecture or using a different toolchain. You can use the @file@ command to verify if it was pro... - HB 10:47 AM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: Communication EGD or ModBus/TCP Cores
- Hi,
Well I have *.so* and a *.la* file, the _dinamic library_ and the _static library used by the GNU "libtools" package._
I tried to add the libmodbus with the .so file to the linker following the wiki for adding dsplink.lib file...
07/26/2016
- AB 04:41 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: Communication EGD or ModBus/TCP Cores
- Hector,
Concerning the Vivado question:
At this time we do not recommend using Vivado as it does not support the Spartan 6 based devices. We recommend Xilinx ISE 14.X and frankly to begin with you can start with their free webpack ... - JC 04:22 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: Communication EGD or ModBus/TCP Cores
- I would have expected you to get either get a .a or .so file.
http://stackoverflow.com/a/12237595
https://stackoverflow.com/questions/8332460/how-do-i-include-a-statically-linked-library-in-my-eclipse-c-project - HB 04:16 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: Communication EGD or ModBus/TCP Cores
- I added the library and its path, but I did not get any .lib file after the library installation, Should I have a .lib file?
I only got some "modbus..".h files and one .pc file - JC 02:59 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: Communication EGD or ModBus/TCP Cores
- Hector Bojorquez wrote:
> Hi Jonathan and Alex,
> ...
Did you add the library to the linker? See the following link for how we add the dsplink.lib file. https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/DSP_Hello_W... - HB 02:33 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: Communication EGD or ModBus/TCP Cores
- Hi Jonathan and Alex,
It is really helpful information, thank you.
I did not know about libmodbus library, now I'm trying to use it but it looks like the compiler is not linking correctly the modbus library, I added the library pat...
07/20/2016
- AB 03:21 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: Communication EGD or ModBus/TCP Cores
- Hector,
I spoke with Jon C. about this issue and we have a little more followup.
In the past for the MitySOM/DSP-L138 family of modules we have utilized Modbus/TCP however it was implemented on the ARM processor in Linux using the ... - JC 10:16 AM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: Communication EGD or ModBus/TCP Cores
- Hector Bojorquez wrote:
> Hi,
> ...
Most likely it is possible, though i'm only briefly aware of how Modbus works and don't know EGD.
>
> ...
Don't think we have dealt with any. A brief google search doesn't show much other than th... - Hi,
I'm a beginner with FPGA and embedded systems, now I'm creating a communication between some devices and the MitySOM1810 through EGD and ModBus/TCP communication protocols.
After this stage we are thinking about implementing th...
07/12/2016
- JC 09:02 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: SPI1 controller, access to FLASH and carrier board. NOT linux based.
- Excellent glad you got it working.
- IS 12:16 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: SPI1 controller, access to FLASH and carrier board. NOT linux based.
- Johnathan,
Joy Joy, Happy Happy.
Everything is working. There were three items altogether. First was the "open drain" on the chip select. The EE added a pull up resistor and that worked). We were able to finally capture the spi si...
07/11/2016
- FW 05:06 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: L138 dsplink problem - schedule while atomic bug
- I looked deeper into the error we were provoking on our bench; it turned out to be a c++ vector de-referencing error that was causing an invalid page fault. The error message posted above appears to be secondary fallout. I'm thinking tha...
- AD 09:41 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: 5CSX-H6-53B-RC with PCIe Hard IP (Root)
- Hi Tom,
As the Root Port, the HPS will control the reset to the PCIe. This can be an HPS GPIO, loaned pin, or FPGA I/O. A bank 8A pin is acceptable.
- Adam - TC 09:02 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: 5CSX-H6-53B-RC with PCIe Hard IP (Root)
- After a bit of rearranging, I've gained the use 179 (B8A_RX_T1_N/CLK7n) for the PERSTn. I believe that should work fine.
Thanks,
Tom. - TC 08:37 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: 5CSX-H6-53B-RC with PCIe Hard IP (Root)
- Hi Adam,
Thanks, I hadn't realised that restriction was just on CvP. As we don't need that, you say that any IO can be used.
Would HPS_GPIO44 (pin244 on the MitySOM) be usable if I set up HPS loaning for that pin so that the FPGA c... - AD 08:11 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: 5CSX-H6-53B-RC with PCIe Hard IP (Root)
- Hi Thomas,
The Cyclone V has a mode where it can be configured using CvP (Config via Protocol) - this configures the FPGA over the PCI Express bus interface. To use this mode, the PERSTN has only one option for the pin location. For...
07/09/2016
- Hi,
We are considering one of the MitySOM boards for use in one of the projects we are working on. I'm currently going over the pin mappings to make sure that we have enough pins.
I was reading through the design guide for the boar... - JC 06:24 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: SPI1 controller, access to FLASH and carrier board. NOT linux based.
- Ian St. John wrote:
> Can you confirm that the signal marked as 'reserved' just beside the SPI1_CSC1 is the SPI1_CSC0 and would that show the chip select operation from reading the flash? It seems a good inference but it is speculative ... - IS 05:56 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: SPI1 controller, access to FLASH and carrier board. NOT linux based.
- Hmm. I asked the EE about the diagram and he was interested in the fact that there was a pull up on the CS line. Apparently, none of our documents state that the SPI1_SCS[1] is "open drain".
We have
"am1808 tech ref (spruh82a)".pdf... - IS 12:40 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: SPI1 controller, access to FLASH and carrier board. NOT linux based.
- The eeprom is on the i2c0 bus. I'm assuming you are talking about the SPI Nor flash which is on SPI1_CS0.+
Oops. Sorry, I said eeprom when I meant the 8MB flash. The JEDEC result is from FLASH, so ok. I modified the code to do the ... - MW 01:23 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: L138 dsplink problem - schedule while atomic bug
- Hi Fred,
Syslink is newer than DSPlink, though in the context of the L138 it's very similar code (syslink evolved from DSPlink).
I am curious about the "sudden" appearance of the error following a power cycle on your fielded unit. ... - FW 12:11 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: L138 dsplink problem - schedule while atomic bug
- The error collected above was on the bench after making some minor software changes seemingly unrelated with the code that accesses dsp-link; the one below was just found in the field. The field device was in operation for 2 months with ...
- FW 11:23 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: L138 dsplink problem - schedule while atomic bug
- I found the following on the TI site; looks like they struggled with this issue with sys-link... I'm not sure how sys-link is related to dsp-link (newer, older, ?)...
[[https://e2e.ti.com/support/embedded/tirtos/f/355/t/385081]]
07/08/2016
- I think there may be a bug in the dsplink kernel code that causes the scheduler to run after a call to spinlock. "remove_wait_queue" seems to be in atomic code, and anything that can cause a call to the scheduler is not allowed after a s...
- JC 09:33 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: SPI1 controller, access to FLASH and carrier board. NOT linux based.
- Ian St. John wrote:
> I am building and programming a custom board without Linux. Basic embedded drivers running from SPI1,CS0 (8MB NOR Flash).
> ...
The eeprom is on the i2c0 bus. I'm assuming you are talking about the SPI Nor flash...
07/07/2016
- DV 11:26 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: /sys/class/fpga-bridge directory is empty
- Thank you for letting us know about this, it was a bug that was caused by some updates to the ethernet driver, which in turn caused some changes in the dtsi. I've pushed the fix to our git repo, it converts how the reset manager was inte...