Mity CPU Platforms

03/01/2017

JK 06:16 PM MitySOM-5CSX Altera Cyclone V Software Development: SPI Comm - can transmit data from Linux, but not receive

Context:
- Hardware: MitySOM 5CSX board connected to another board containing several chips which communicate via SPI
- Software: the MitySOM processor is running the Altera Linux 4.1.22 LTSI RT kernel with a device tree I've customize... Jared Kirschner

JC 02:03 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Setting up MityDSP-L138 for Hello World program

Hi Artem,
What version of Code composer are you using? Also what MDK version? Jonathan Cormier

02/22/2017

MR 10:27 PM MitySOM-5CSX Altera Cyclone V PCB Development: Standoff on Mounting Hole Locations page

I believe there is a small errata on the [[Mounting_Hole_Locations]] page.
At the bottom it states... "Standoff: McMaster Carr PN - 91115A510" ... This is not an actual part number in McMaster.
I think the last two numbers where switch... Michael Ruen

AK 05:58 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: Setting up MityDSP-L138 for Hello World program

Good day,
I'm trying to set up the “DSP Hello World” from the Wiki instructions (https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/DSP_Hello_World). “Compiling for the ARM” was ommited, as the main goal is to run ... Artem Khotab

02/17/2017

JC 02:00 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: Problems building the Kernel

Your right I can't find the u-boot-tools archive anymore.
Luckily the mkimage tool is built by u-boot. So it can be copied to the system so its available in the path.
Instructions partially from https://support.criticallink.com/red... Jonathan Cormier

HB 01:39 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: Problems building the Kernel

Hi Jonathan,
We followed the instructions in the link, but we continue having problems to get the U-boot-tools package, it updated some other things, but we got this error:
*W: Failed to fetch http://ppa.launchpad.net/u-boot-tool... Hector Bojorquez

JC 12:34 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: Problems building the Kernel

We are working on releasing new versions of the VM. In the mean time you can change the repos so they point to the "old-releases".
http://askubuntu.com/questions/91815/how-to-install-software-or-upgrade-from-an-old-unsupported-release?... Jonathan Cormier

HB 12:32 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: Problems building the Kernel

Hi all,
I´m trying to do the "FPGA GPIO Core Example":https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/FPGA_Core_Device_Drivers#FPGA-GPIO-Core-Example
In the step #1 "Load an FPGA image with a GPIO core componen... Hector Bojorquez

JC 12:32 PM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: MitySOM_335x VIO_1P8 Tolerance

Its mode pin is grounded. Jonathan Cormier

JC 12:31 PM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: MitySOM_335x VIO_1P8 Tolerance

The VIO_1P8 is driven by a TPS62290DRVT regulator. See here http://www.ti.com.cn/cn/lit/ds/symlink/tps62290.pdf Jonathan Cormier

12:09 PM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: MitySOM_335x VIO_1P8 Tolerance

What is the range of voltages (tolerance) on the VIO_1P8 output supply on the SOM. We are using it as the VREFP for the ADC? Anonymous

02/15/2017

JA 10:28 AM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: MitySOM-1810F PROFIBUS Development kit: Programming uart.ngc file in FPGA Spartan 6.

Hello, good day,
I am working with the MitySOM-1810F PROFIBUS Development kit which includes the AM1810 ARM Microprocessor For PROFIBUS and Spartan 6, I would like to implement the UART core for FPGA which is located in:
\fpga\cor... Jesus Alejandro Alvarez Trejo

02/14/2017

JA 09:24 AM MityDSP-L138 (ARM9 Based Platforms) PCB Development: RE: FPGA CLOCK LOCATION

Hello, Good day
Thank you for the answer, I have been working only with the FPGA without using the EMIF interface between the L138 and FPGA.
I want to implement a code done in VHDL and my design contains a clock in its operation l... Jesus Alejandro Alvarez Trejo

02/08/2017

SS 10:16 AM MitySOM-5CSX Altera Cyclone V PCB Development: Thermal Management, Datasheet Table 6, Commercial or Industrial

Hello,
Regarding Table 6 in the datasheet, is this information valid for the commercial or industrial temperature range modules?
Thanks a lot,
Steve Stephen Snyder

02/02/2017

AD 12:57 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: CLK2DDR signal on development board

Hello Franco,
Thanks for checking before committing to the board... The I/O standard does indeed sound like a mismatch!
The likely difference between the 2.5V I/O design building and a failing 3.3V I/O design is due to the (VPD) P... Adam Dziedzic

FS 11:47 AM MitySOM-5CSX Altera Cyclone V FPGA Development: CLK2DDR signal on development board

Hi, I'm designing my own carrier card, but I've some doubts about the use of the bank 4A.
I need to connect the the mitysom module some parallel DACs with 3.3 volts single ended levels as outputs.
I need about 34 pins so I was planning... franco spinella