![]() ![]() | Structure for alarm queue |
![]() ![]() | Structure defining buffer and size |
![]() ![]() | Cache-list header structure |
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![]() ![]() | Instances of this class handle access to a Analog Devices Ad56x5 digital-to-analog converter via the generic I2c interface for the MityDSP |
![]() ![]() | Instances of this class create an interface to an ADS1278 24-bit analog to digital converter |
![]() ![]() | Instances of this class create an interface to an ADS7844 12-bit analog to digital converter |
![]() ![]() | Instances of this class create an interface to an ADS834x 16-bit analog to digital converter |
![]() ![]() | Instances of this class handle |
![]() ![]() | Simple configuration structure that may be used when initializing a tcDspAdcBase derived interface class |
![]() ![]() | A utility class to manage the automatic release of LCK's |
![]() ![]() | Instances of this class handle configuring, and enabling the MityDSP Arbitrary Waveform Generator core I/O interface |
![]() ![]() | Instances of this class handle configuring, and enabling the MityDSP Dual Arbitrary Waveform Generator core I/O interface |
![]() ![]() | Used to change the currently selected Flash bank |
![]() ![]() | Static class to provide application level wrappers for reprogramming MityDSP application and bootloader FPGA and DSP images from a running application |
![]() ![]() | Static class to provide access to the MityDSP CLUB Bootstrapper to load a new executable |
![]() ![]() | Singleton that manages a set of standard buffer pools ranging in size from 16 bytes to 64K bytes |
![]() ![]() | Instances of this class handle |
![]() ![]() | Thread safe circular buffer interface supporting arbitrary size and arbitrary read/write requests |
![]() ![]() | Maintains a circular index and manages the read and write pointers |
![]() ![]() | Instances of this class handle an interface to the frequency-adjustable HW clock core, based upon Appendix G of RFC-1305 (NTP) |
![]() ![]() | This is a singleton class |
![]() ![]() | Used to interface to the MityDSP event counter core |
![]() ![]() | Used to set up and receive data from a Crystal CS552X family A-to-D converter |
![]() ![]() | Instances of this class create an interface to an ADS834x 16-bit analog to digital converter |
![]() ![]() | Instances of this class handle access to a TI DAC8534 digital-to-analog converter via the generic SPI interface for the MityDSP |
![]() ![]() | Instances of this class handle access to an Analog Devices AD420 digital-to-current loop converter via the generic SPI interface for the MityDSP |
![]() ![]() | Base class for digital-to-analog converter devices using the MityDSP McBSP interface |
![]() ![]() | Allows the user to draw, erase, write text and bitmaps on a simple memory mapped display interface |
![]() ![]() | Base class to provide generic access to a display frame buffer via the tcDspFpgaDma class |
![]() ![]() | Handles formatting and reporting errors in a consistent manner |
![]() ![]() | Static class to provide access to core-independent features of the MityDSP firmware |
![]() ![]() | Allows various fixed and proportional fonts to be defined for use (with tcDspDisplay, for example) |
![]() ![]() | MityDSP FPGA with DMA access to blocks of DSP memory |
![]() ![]() | Instances of this class handle configuring and setting up the coefficients for the IIR Filter core |
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![]() ![]() | Instances of this class handle sending, receiving, and configuring a register containing 32 general purpose I/O pins |
![]() ![]() | Instances of this class handle an interface to the high-speed USB device This device is theoretically capable of speeds up to 400 Mbps |
![]() ![]() | Instances of this class handle access to a "generic" implementation of the I2C interface for the MityDSP |
![]() ![]() | Instances of this class handle access to a "generic" implementation of the I2C interface, version 2.0, for the MityDSP |
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![]() ![]() | Static class to provide interrupt dispatching capabilities for the external interrupt pins (levels 4-7) of the MityDSP |
![]() ![]() | Instances of this class handle access to a "generic" implementation of the LVDS interface for the MityDSP |
![]() ![]() | The tcDspMcbsp class is used for communications via the Texas Instruments Multichannel Buffered Serial Port (McBSP) |
![]() ![]() | The tcDspMcbspConfig class provides a simple initialization structure for purposes of configuring a tcDspMcbsp class instance |
![]() ![]() | Class used to create an output latch interface (for use as a chip selector or other control line) |
![]() ![]() | This class provides a base class from which various MityDSP parsers may be derived |
![]() ![]() | Used to interface to the MityDSP pulse integrator core |
![]() ![]() | Instances of this class handle configuring, and enabling the MityDSP Pulse Width Modulator core I/O interface |
![]() ![]() | Simple initialization structure for the purposes of configuring a tcDspPwm core class instance |
![]() ![]() | Instances of this class handle sending, receiving, and configuring Quick DMA tranfers |
![]() ![]() | Virtual base class to provide consistent access to various firmware cores that adhere to the RAM Block interface |
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![]() ![]() | Virtual base class to provide consistent access to various real-time clock devices |
![]() ![]() | Instances of this class handle sending, receiving, and configuring a serial port |
![]() ![]() | Instances of this class handle access to a "generic" implementation of the SPI interface for the MityDSP |
![]() ![]() | Instances of this class handle configuring, and enabling the MityDSP base Stepper Motor Controller core I/O interface |
![]() ![]() | Simple initialization structure for the purposes of configuring a tcDspStepper core class instance |
![]() ![]() | Base class to define a consistent set of interfaces for all storage devices |
![]() ![]() | Virtual base class to provide consistent access to various thermistor devices |
![]() ![]() | This class is the MityDSP timer object |
![]() ![]() | Used to interface to the MityDSP Timing Generator core |
![]() ![]() | Used to set up and receive data from a TI TLV254X family A-to-D converter |
![]() ![]() | Access to a 4-wire touch screen overlay device |
![]() ![]() | Static class to provide the ability to enable and manage the watchdog timer core of the MityDSP |
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![]() ![]() | 16384 Hz Chop Frequency |
![]() ![]() | Command Register (8-bits) - with CB = 1 |
![]() ![]() | This structure is used to define a ROM filesystem node |
![]() ![]() | This structure is the mailbox message structure passed up by the FrameCapture logic to calling applications |
![]() ![]() | LCD timing configuration structure |
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![]() ![]() | Structure used to store screen coordinates (in pixels) |
![]() ![]() | Structure used to store screen offsets (in pixels) |
![]() ![]() | Mapping of sectors to addresses |
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![]() ![]() | ATA Error Register |
![]() ![]() | ATA Status Register |
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![]() ![]() | Command Register (8-bits) |
![]() ![]() | Configuration Register (24-bits) |
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![]() ![]() | The tuFifoData union defines the data bits sent to or received from the SPI FIFOs |
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![]() ![]() | This union represents the camera link FIFO data |
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![]() ![]() | This structure defines the header for all LVDS data packets |
![]() ![]() | Trailer added to end of messages placed in RX FIFO |
![]() ![]() | Status information returned by MMC card |
![]() ![]() | This union defines the timing generator OpCode RAM vector that is used to generate patterns by the internal state machine |
![]() ![]() | Definition of sample data holding area |
![]() ![]() | Definition of sample data holding area |
![]() ![]() | Set-Up Register (24-bits) |
![]() ![]() | The tsUsbBuffer structure is used to provide internal buffering for incoming and outgoing data |