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Communicating with an 8-bit parallel interface (GPIO, SPI or GPMC)
Added by Alexander Block about 10 years ago
Posting this on behalf of a customer:
The interface to their networking chip and other peripheral boards on their current motherboard is through memory mapped I/O. The customer would like to recreate this with the MitySOM-335x and is exploring the options available to them both in general with the MitySOM-335x and with respect to any development board limitations for a proof of concept.
I've experimented with userspace GPIO and I can toggle pins at 300kHz which might be fast enough, but implementing a bi-directional 8 bit data bus with 8 discrete GPIO pins would be very messy. I looked into the GPMC pins that are available on the Expansion I/O connector. You had said that only pins AD8 - AD15 would be available as GPIO pins, which made me wonder if you are using that memory bus for some flash on the MitySOM module.
The module being used currently is a 3354-HX-X38-RC which has 512MB of NAND memory on the GPMC bus. For this reason it was stated that only AD8 through AD15 would be available as GPIO pins. If a memory maped device is used then you can utilize the GPMC control signals and AD0 through AD7 for that device in addition to a new chip select. All of these pins are available from the dev board on J700.
Would I be able to use that connector (J700) for external memory mapped I/O? Would I be able to slow down the memory access cycle times to work with my peripherals without messing up what you have on the MitySOM? If I can use it, do you have any example code to access absolute addresses from a userspace program? I am also looking into using an SPI port to handle the 8-bit data bus in combination with GPIO pins. I'm currently stuck trying to create a /dev/spiB.C (B=bus, C=chip select) device. Do I need to edit a device tree .dts file somewhere?
Replies (3)
RE: Communicating with an 8-bit parallel interface (GPIO, SPI or GPMC) - Added by Jonathan Cormier about 10 years ago
As Alex mentioned the GPMC bus is used for an on-SOM nand memory. The GPMC bus allows multiple devices to use the bus as long as they only communicate when their chip select is high. Does your device have someway to ignore communications when a chip select is not active?
I'm not familiar with how precisely the GPMC bus works with non-nand peripherals but the section in the manual is fairly detailed. Please read up in the technical reference manual Section 7.1.
As far as accessing it from user space. This would depend on how much kernel driver support there is for this use case. The nand driver makes the device show up as a mtd block device but probably won't work for your case. Please read the GPMC section and let me know if you think the underlying hardware can do what you want and then I'll try to help you look at the current driver situation.
RE: Communicating with an 8-bit parallel interface (GPIO, SPI or GPMC) - Added by Jonathan Cormier about 10 years ago
SPI:
I'm not sure what you mean by using the spi bus to handle the 8-bit data bus.
If you want raw access to the spi device then you need to modify the baseboard file. The 3.2 kernel we are using doesn't use device tree, instead there are board files which setup the drivers in use.
The spidev driver allows for userspace access to a spibus on a specified chip select. We've used this driver on our L138 SoM. You'll need to enable the driver in the kernel menuconfig. It is located under "Device Drivers" -> "SPI Support" -> "User mode SPI device driver support". Reference Linux_Kernel for building the kernel and menuconfig.
Example of enabling spidev in baseboard file:
http://support.criticallink.com/gitweb/?p=linux-davinci.git;a=blob;f=arm/mach-davinci/baseboard-industrialio.c;h=112cbf0f19942494dd521adaf5e8bf411a6a7f3a;hb=refs/heads/mitydsp-linux-v3.2#l333
Note this file is from the L138 kernel
335x baseboard file:
http://support.criticallink.com/gitweb/?p=linux-mityarm-335x.git;a=blob;f=arch/arm/mach-omap2/baseboard-mityarm335x-devkit.c;h=65d594c62a960ea07d447592e1282daf03609280;hb=HEAD#l475
Kernel documentation on spidev:
http://support.criticallink.com/gitweb/?p=linux-mityarm-335x.git;a=blob;f=Documentation/spi/spidev;h=ed2da5e5b28a4490a3b03787b02df66d083692be;hb=HEAD
Kernel example userspace app for spidev:
http://support.criticallink.com/gitweb/?p=linux-mityarm-335x.git;a=blob;f=Documentation/spi/spidev_test.c;h=16feda9014692a87a4996bf51d759ab9e7500ee5;hb=HEAD
RE: Communicating with an 8-bit parallel interface (GPIO, SPI or GPMC) - Added by Alexander Block about 10 years ago
Updated question(s) from the customer:
I've been looking into using GPMC. The Technical Reference Manual for the AM335x says that GPMC has a 512MB address space. Since the module I have has a 512MB NAND flash on GPMC, configuring another chip select to control my hardware interface within that same address range would generate a fault. But you advertise a maximum of 1GB NAND flash on this module. I'm puzzled about how this is possible. I found basically the same question on a TI wiki page (http://e2e.ti.com/support/arm/sitara_arm/f/791/t/282915.aspx ) where a TI employee suggests using a GPIO pin to switch between 2 - 512MB memories. Is this how you manage to get 1GB of Flash on this module? This would allow you to use the same GPMC chip select for both flashes, but that leaves me with the problem of how to configure a different chip select within the same address space. I believe your WiFi adaptor is also in the same GPMC address space. How is that chip select configured?
Answer(s):
1) With NAND devices the GPMC address 'A' type pins are not used for the addressing as it issues the address over the Data 'AD' pins. Because the NAND is not memory mapped the limit (per the TRM table 26-14) is not 512MB but 8GB. This post covers max NAND size vs the GPMC address sizes: http://e2e.ti.com/support/arm/sitara_arm/f/791/t/163815.aspx
2) With the "GPMC" mode the 512MByte maximum is across all 8 chip selects, a single device/chip select is limited to 512Mbit. (Page 620 TRM)
Followup Question:
We need to understand how you plan on using the GPMC interface for your custom device/driver and do you plan on needing/using the NAND memory as well.
