Ethernet PHYs
Added by Anonymous about 12 years ago
Please correct me if I'm wrong, but it appears the pin-muxing configuration for the MityARM-335x SOM is forcing the use of an RGMII type interface for connecting up to Ethernet PHYs. For port 1, most of the interface pins are available except for the GMII1_RXER pin which is assigned to I2C1_SCL and the GMII1_CRS pin which is assigned to I2C1_SDA (I2C1 is connected to the Configuration EEPROM and the PMIC so cannot be reassigned). For port 2 there is a similar situation where most of the interface pins are again available except for the GMII2_RXER pin which is assigned to GPMC_WPN and the GMII2_CRS pin which is assigned to GPMC_WAIT0 (these GPMC pins are used in the NAND Flash interface and cannot be reassigned).
Without the use of these signals, specifically the RXER signal, the Ethernet ports cannot be configured for the MII or RMII type interfaces used in the lower cost 10/100 PHYs. The only PHYs I've found that use the RGMII interface are the more expensive higher performance 10/100/1000 PHYs.
If anyone knows of a way around this or of industrial temp 10/100 PHYs that use an RGMII interface, I would be interested in knowing the details.
Replies (4)
RE: Ethernet PHYs - Added by Michael Williamson about 12 years ago
What other peripherals are you trying to accommodate? At a glance it looks like the pin outs should support RMII0 on the LCD_DATAXX pins, but if you need the LCD interface. Can you list what peripherals you need?
-Mike
RE: Ethernet PHYs - Added by Anonymous about 12 years ago
Hi Mike,
The interfaces we definitely need out of the 335x are a 16 bit GPMC (to FPGA), 1 Ethernet (10/100 is fine), 2 USBs, 2 UARTs and 1 SPI. I'd like to keep the 16 bit LCD interface available but could use those pins for other things if I had to.
I looked at the LCD-DATAxx pins and it looks like you are referring to a mode 2 pinmux setting on those pins. These MII0 pins have a "PR1_" prefix in the signal name. I thought the "PR1_" at the beginning of the signal names means it's a function for the Programmable Real Time Unit (PRU). I didn't think these signals could be used for the CPSW module driven by the Cortex-A8 engine.
Thank you for your help.
Mark
RE: Ethernet PHYs - Added by Michael Williamson about 12 years ago
Hi Mark,
You are correct about the PR1_MII* signals, according to this E2E post, sorry about that.
http://e2e.ti.com/support/dsp/sitara_arm174_microprocessors/f/791/p/206939/733857.aspx
I am just looping back to this, so I can't confirm yet if design of an RMII or MII interface is a problem or not, though you seem to be tracking the issue properly.
-Mike
RE: Ethernet PHYs - Added by Michael Williamson about 12 years ago
Hi Mark,
I don't see a way around this at the moment. It does indeed look like you need to use the Gigabit Phy interface with the MityARM-3359 module.
Unfortunately, all of our initial use-cases involved Gigabit Ethernet requirements and we missed this configuration need in the module design. We're looking to see if there is a simple solution we might be able to apply going forward, but I cannot say if this will be addressed or not in the near future.
Sorry.
-Mike
