Hardware Design Guidelines¶

The table below includes relevant links for host (carrier) board design guide documents for the MitySOM-335x Family of SoMS.

Module	PCB Design Guide Document
MitySOM-335x	Design Guide

Other notes¶

• Do not plan to use I2C2 as it is used on-module by the AM335x to access the power management IC.
• I2C1 can be used outside of the module however the pin-mux location for the interface should not be changed as it is tied to the EEPROM and PMIC.
• Make sure that the mounting tabs for the DDR3 204-pin connector are a part of the footprint for your connector symbol.
• SPI1 signals on the edge connector must be used for SPI1 if the module has SPI-NOR memory. If not these pins can be used for the other pin-mux functions available on them.

Unconnected / No Connect Pins from Module¶

For any pins that are on the edge connector of the MitySOM-335x module and are unused on a custom carrier board the following recommendation is made by TI:

Signals on interfaces that are unused can typically be left as no connect. Many of the IOs have a Pad Control Register
(see Chapter 9 of the TRM for more details) which gives control over the input capabilities of the I/O (RXACTIVE field in each conf_<module>_<pin> register).
Software should disable the I/Os which are no connects (ie, RXACTIVE=0) as soon as possible in initialization.
This RXACTIVE field defaults to "input active" for most signals, which means there is a potential for some leakage
during powerup of the chip if the input floats to a mid-supply level before the software can initialize the I/O. 
This should only be a concern if you are attempting to power up the design with a minimum power consumption. 
Most designs should be able to tolerate this small amount of leakage in each floating I/O until the software 
has a change to disable it. After disabling the I/O, no leakage will occur.

For example based on this recommendation an entry in your baseboard.c file would look similar to the following:

-        {"gpmc_ad15.mmc2_dat3", AM33XX_PIN_INPUT_PULLUP}, / * Enabled as mmc2_dat3 */
+        {"gpmc_ad15.gpmc_ad15", AM33XX_PIN_OUTPUT}, /* Disable pin gpmc_ad15 */

As seen using the "0" mode option is ideal as that mode is unique to each pin. Another option is to use the GPIO mode "7" for each pin as that is also unique. You do not want to get into a scenario where you define two pins in the design with the same mode, i.e. mmc2_dat3 on gpmc_ad15 ("disabled") and gpmc_be1n where you want to use MMC2.

Schematic Checklist Guidelines from TI¶

The following wiki page from TI lists a complete schematic checklist when doing a processor design with the AM335x CPU. Note that some of this information may not be relevant as it has been handled on the module. However it may still be a good source of information for custom carrier boards for many/most of the MitySOM-335x edge connector pins.

http://processors.wiki.ti.com/index.php/AM335x_Schematic_Checklist