MitySOM-335x RTC Information¶
RTC Kernel Configuration¶
Critical Link has found that the best method of providing an RTC on the MitySOM-335x is by using the TPS65910 PMIC RTC as it reduces battery current draw as documented below.
Note: Because of the higher current draw, the SOM powers the AM335x RTC from a separate 1.8V regulator powered by VIN. It is not connected to VBACKUP and thus will lose power when the system is shut off. As such the AM335x RTC cannot be used for battery-backed timekeeping.
Note: that the default init scripts included in our kernel/file system utilize the rtc0 device. If both the PMIC and AM335x RTC's devices are enabled and built into the kernel, the PMIC will be rtc1 and the AM335x will be rtc0. We recommend you building the AM335x RTC as a module in the Kernel and building the PMIC RTC into the kernel, which will thus present as rtc0. The AM335x RTC will end up as rtc1 since it won't be loaded until userspace loads the kernel modules. commit
You should modify your kernel configuration to enable the TPS65910:
CONFIG_RTC_DRV_TPS65910=y
Also, you want to build the AM335x RTC ("OMAP") as a module
CONFIG_RTC_DRV_OMAP=m
With the Kernel rebuild a message similar to the following should be seen during boot:
tps65910-rtc tps65910-rtc: rtc core: registered tps65910-rtc as rtc0
Further details about the RTC on the MitySOM-335x can be found in the "PCN20121113000.pdf" PCN here: https://support.criticallink.com/redmine/projects/armc8-platforms/wiki/Module_Product_Change_Notifications
VBACKUP (PMIC RTC Backup) Current Draw¶
Measurements were taken using a 3V supply in place of a coin cell battery using the MityARM-335x development kit with an 80-000509RL-1C MityARM-3359 board (DDR2, 256 MB).
With 3.3VIN applied, current consumption measured was less than 1 micro amp (limited by test equipment).
With 3.3VIN powered down and the PMIC RTC enabled and active, the current consumption of the VBACKUP was measured at 10.2 micro amps.
Recommended RTC input voltage¶
The RTC battery backup design of the 335x module is meant to support a 3V button cell battery. It is recommended that the voltage going into the "VBACKUP" pin be at least 2.5V to guarantee RTC operation.
Minimum Recommended: 2.5V
Maximum Recommended: 3.6V
Development Kit SD card time restoration¶
The SD card that is shipped with our MitySOM-335x development kits creates a file during shutdown (poweroff or restart) in which the current time is stored/updated: /etc/timestamp
The script that writes this is /etc/init.d/bootmisc.sh
SOM PMIC Power Off¶
In order for the SOM to power off, the PMIC needs to enter the OFF or BACKUP state. To accomplish this the PMIC's PWRHOLD pin needs to go low.
Note you need a Rev4+ Som for this to work. See PCN: https://support.criticallink.com/redmine/attachments/download/13652/PCN20170130000.pdf
AM335x Ball C6 (PMIC_POWER_EN) is connected to PMIC Ball 1 (PWRHOLD)
The AM335x PMIC_POWER_EN pin is connected to the AM335x RTC. So in order for this pin to go low at shutdown the omap_rtc driver needs to be configured as a system-power-controller and the omap-rtc driver needs to be loaded.
&rtc { system-power-controller; };
For the 3.2 kernel¶
am335x_rtc_info.pm_off needs to be set to true in the board-mityarm335x.c file.
static struct omap_rtc_pdata am335x_rtc_info = { .pm_off = true, .wakeup_capable = 0, };
SOM Sleep/Standby support¶
Please contact Critical Link if your design requires sleep support
Baseboard hardware requirements:- PWR_ON and EXT_WAKEUP shall be connected to a push button
See PCN Figure 1: https://support.criticallink.com/redmine/attachments/download/13652/PCN20170130000.pdf - PMIC_SLEEP shall be connected to a bank 0 GPIO
Allows SOM to reduce PMIC power usage.
Ideally, use GPIO0_19 as the M3 power code toggles this pin already. Forum - PMIC_INTL shall be connected to a bank 0 GPIO
Allows PMIC TPS65910 RTC to wakeup SOM on an alarm - Any external interrupt that wants to wake the system from sleep needs to be connected to a bank 0 GPIO
- Pinmuxes need to be carefully set up to ensure minimal power usage
https://web.archive.org/web/20210114161918/https://processors.wiki.ti.com/index.php/Optimizing_AM335x_IO_Power_in_DeepSleep0 - LED_RTN needs to be controllable or NC (VAUX2 LED uses ~16mW during sleep)
Bank 0 GPIOs are gpio0[0]
to gpio0[31]
. This bank is the only gpio bank that is left powered on when in sleep.
https://web.archive.org/web/20181024030724/http://processors.wiki.ti.com/index.php/AM335x_Schematic_Checklist#Low_Power_considerations
Lots of debug info in this forum post: https://e2e.ti.com/support/processors/f/processors-forum/464240/optimizing-am335x-io-power-in-deepsleep0#pifragment-322104=2
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