System Design Overview¶

• Table of contents
• System Design Overview
  • Preloader

Designing a system with the MityARM-5CSX module is a more involved than using other System On Module designs due to the integrated CPU/FPGA feature.

Each project will require you to create/customize the following items (in addition to your main application / system code):

• Quartus project ( <project.qpf> )
• QSys project ( <project.qsys> )
• Preloader ( Generated by Altera tools )
• Device Tree ( <project.dts> )

Also, you will likely need to develop/modify:

• Device drivers ( if devices are not currently supported )
• Startup scripts ( usually copied from an existing script )

Preloader¶

The preloader is the 2nd stage bootloader (the first stage bootloader is the ROM bootloader in the Altera part). Its primary functions are:

• Configure the I/O pin mux settings.
• Configure the DDR3 RAM controller.
• Load and execute u-boot.

Because the preloader configures the pinmux and DDR controller, Altera uses their qsys (formerly sopc-builder) tool to configure everything.
The basic steps to generate the preloader are:

1. Launch quartus.
2. Create a new project or start from the Critical Link MityARM-5CSX reference project
   • The CL reference project has the top-level entity and HPS preipherals set up already (for on-som peripherals)
3. Launch the Qsys tool (from Quartus Tools menu)
4. Open the MityARM-5CSX reference qsys project (or your qsys project)
   • If not already done, be sure to add the path to the Crtiical Link IP folder to the IP search path (Tools->Options->IP Search Path)
   • Internal (CL) SVN mityaltera/mityarm-5csx/trunk/hw/fpga/ip
5. Configure / Verify all pinmux settings in the Hard Processor System
   • double click on the hps_0 component to open it.
   • If you have started with the CL reference project (or applied the CL HPS preset), the basics will be configured already. Do NOT change SDRAM settings!
6. Add any required pinmux settings.
   • Do NOT change Ethernet, QSPI, USB1 UART0, or I2C0 settings, as they are used by the MityARM-5CSX module
7. After adjusting / verifying system settings in qsys, go to the generation tab and click the :Generate" button.
   • This will create the system design files for quartus.
   • You can now close the Qsys application
8. Back in Quartus, you need to build the project (Processing->Start Compilation or the toolbar button).
   • Depending on the complexity of your design, this step can take a while.
9. Assuming your compilation was successful, the tools will generate an hps_isw_handoff folder with required settings data.
10. Run the BSP editor (bsp-editor)
11. Select File->New BSP and select the following:
    • Preloader settings directory (click the ... button then navigate to and select the hps_isw_handoff/<..._hps0> folder.
    • You should be able to leave the other settings as their defaults.
12. The next window allows you to customize the preloader settings. The definition of each settings is detailed in the Altera documentation. The only thin you really may need to change is the BOOT FROM setting.
    • Make sure you only pick one boot mode, or the preloader will not compile!
13. Click Generate. The BSP Editor will create a software/spl_bsp folder to build the preloader in.
14. You can now cd to the newly created director and make the preloader.
15. cd to the spl direcory, and make the preloader
    • cd software/spl_bsp/uboot-socfpga
    • make
    • You should be left with a preloader-mkpimage.bin file, which is actually multiple copies of the preloader concatenated together, ready to be burned to your boot media.

Updated about 1 year ago by Daniel Vincelette