Mity CPU Platforms

11/13/2014

04:26 PM MitySOM-5CSX Altera Cyclone V Software Development: Kernel Driver

Hi,
I'm trying to lad a kernel driver by following example on this page https://github.com/zhemao/interrupt_example
However, after run "insmod fpga\_uinput.ko" I get the following error.
fpga_uinput: version magic '3.9.0-00161-g... Anonymous

11/12/2014

02:38 PM MitySOM-5CSX Altera Cyclone V Software Development: SOCKIT GSRD

Hi,
For my project, I'm trying to use precompiled Linux libraries with Sockit as seen in this link "http://rocketboards.org/foswiki/Documentation/ArrowSoCKITEvaluationBoardLinuxGettingStarted#Creating_an_SD_Card_using_a_Windows_Host"
... Anonymous

11/10/2014

DG 01:52 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Real time SATA writes

Hi Mary,
As you suspected in your original post, it is likely that when you are calling fwrite, in some cases the write cache is full and is causing full flush down to storage (NAND). In this case it will take longer than just writing... Dominic Giambo

MF 01:04 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Real time SATA writes

After further testing and setting optimization, I have narrowed down the delay:
The call to fwrite() normally takes about 2.5 msec, but occasionally (on the order of minutes) this call can take 20 msec, 40 msec, 150 msec, or even 300... Mary Frantz

11/07/2014

DV 02:22 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Modular SGDMA

Hi Jack,
We don't have any explicit examples of this but you will want to look into the userspace I/O driver. This should allow you to map in the FPGA interrrupts to a /dev/uio device.
I did a bit of searching and this looks like a... Daniel Vincelette

11/05/2014

01:40 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Modular SGDMA

Hi Dan,
The issue seems to be with the polling. I brought out the empty signal to an oscilloscope and found that it is on, but for some reason I'm not reading that on the software side.
I think it's better to switch to interrupt to... Anonymous

10/31/2014

OM 10:44 AM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: Clock for FPGA

Hi.
I'm using MityDSP-L138F Board. As will ensure that the generated clock signal to FPGA?
Thanks Oleh Mela

10/29/2014

CK 10:58 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Performance problem with baremetal code

In the meanwhile and after an ARM Cortex training I've found the root cause of the problem:
For enabling the caches, you have also to initialize the MMU, e.g. with the attached version of performance.c. Nevertheless the baremetal code... Christian Kempter

10/28/2014

JC 11:48 AM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: RTC Crystal Specifications

Theres a 24MHz crystal between XTALOUT and XTALIN on the ARM. Its frequency tolerance at 25C is +/- 25ppm.
Note these numbers are based on a 3359-GX-226-RL RevD. Jonathan Cormier

CL 11:42 AM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: RTC Crystal Specifications

Great, thank you for the information. Is it a similar specification for the other oscillator on the board, connected to the ARM? Chris Leon

JC 11:31 AM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: RTC Crystal Specifications

For the 32khz crystal attached between the OSC32KOUT and OSC32KIN pins, according to its datasheet, the frequency tolerance at 25C is +-10ppm. Jonathan Cormier

CL 10:56 AM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RTC Crystal Specifications

What are the ppm drift specifications for the TPS65910 RTC crystal? Chris Leon

10/27/2014

AB 04:10 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: Communicating with an 8-bit parallel interface (GPIO, SPI or GPMC)

Updated question(s) from the customer:
I've been looking into using GPMC. The Technical Reference Manual for the AM335x says that GPMC has a 512MB address space. Since the module I have has a 512MB NAND flash on GPMC, configuring anot... Alexander Block

10/24/2014

MW 10:41 AM MityDSP-L138 (ARM9 Based Platforms) PCB Development: RE: L138 SOM LEDs

Sorry,
On Non-FPGA modules:
D1 is connected to R16 (GP6_12) of the OMAP-L138.
D2 is connected to R17 (GP6_13) of the OMAP-L138.
-Mike
Michael Williamson

AK 10:05 AM MityDSP-L138 (ARM9 Based Platforms) PCB Development: RE: L138 SOM LEDs

Hi Mike,
The SOM we are using is the non-FPGA version. What do D1 and D2 connect to?
Thanks,
Anton Anton Kitai

MW 07:22 AM MityDSP-L138 (ARM9 Based Platforms) PCB Development: RE: L138 SOM LEDs

D1 is connected to the FPGA_DONE pin on the FPGA configuration block.
D2 is connected to P15 of the FPGA IO_L74P_AWAKE_1
D3 is connected to P16 of the FPGA IO_L74N_DOUT_BUSY_1
-Mike
Michael Williamson

AK 10:03 AM MityDSP-L138 (ARM9 Based Platforms) PCB Development: RE: MityDSP-L138 Boot Problem

This issue has been resolved - we had left an uterminated SPI1_CLK signal trace on our base board at an unpopulated device.
Anton Anton Kitai

10/22/2014

AK 03:13 PM MityDSP-L138 (ARM9 Based Platforms) PCB Development: L138 SOM LEDs

Please can you provide information for D1 and D2 LEDs on the L138-FX-225-RC module. What are they connected to?
Thanks,
Anton Anton Kitai

AK 02:05 PM MityDSP-L138 (ARM9 Based Platforms) PCB Development: MityDSP-L138 Boot Problem

We are using the L138-FX-225-RC on a new custom baseboard and are having trouble with boot:
- no UART activity in normal SPI boot
- UART boot mode sends "BOOTME"
We attempted to erase and flash the bootloader using the WinCE boot pa... Anton Kitai

10/21/2014

JC 10:28 AM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: Communicating with an 8-bit parallel interface (GPIO, SPI or GPMC)

SPI:
I'm not sure what you mean by using the spi bus to handle the 8-bit data bus.
If you want raw access to the spi device then you need to modify the baseboard file. The 3.2 kernel we are using doesn't use device tree, instead the... Jonathan Cormier

JC 10:16 AM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: Communicating with an 8-bit parallel interface (GPIO, SPI or GPMC)

As Alex mentioned the GPMC bus is used for an on-SOM nand memory. The GPMC bus allows multiple devices to use the bus as long as they only communicate when their chip select is high. Does your device have someway to ignore communicatio... Jonathan Cormier

10/20/2014

AB 04:55 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: Communicating with an 8-bit parallel interface (GPIO, SPI or GPMC)

Posting this on behalf of a customer:
The interface to their networking chip and other peripheral boards on their current motherboard is through memory mapped I/O. The customer would like to recreate this with the MitySOM-335x and is ... Alexander Block

04:34 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Modular SGDMA

Hi Dan,
I polling the FIFO empty signal for the both the dispatcher and write master to ensure that only when both FIFOs are empty when I will continue.
The delay varies, it's hard to predict.
Ideally we don't want to put any sl... Anonymous

10/17/2014

DV 04:53 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Modular SGDMA

Hi Jack,
You could try polling the dispatcher's busy bit instead but I'm not quite sure if that would solve your issue. Any idea at how long the delay is for? Does the FIFO overflow because of it? Also you might want to put a bit of a... Daniel Vincelette

03:57 PM MitySOM-5CSX Altera Cyclone V FPGA Development: Modular SGDMA

Hi
I'm running into a difficulty with the Modular SGDMA that is used in the HPS Memory example.
I have to send dispatchers repeatedly in a infinite loop. I have it designed such that after I send the command to write the dispatcher... Anonymous