Mity CPU Platforms

07/20/2016

AB 03:21 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: Communication EGD or ModBus/TCP Cores

Hector,
I spoke with Jon C. about this issue and we have a little more followup.
In the past for the MitySOM/DSP-L138 family of modules we have utilized Modbus/TCP however it was implemented on the ARM processor in Linux using the ... Alexander Block

JC 10:16 AM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: Communication EGD or ModBus/TCP Cores

Hector Bojorquez wrote:
> Hi,
> ...
Most likely it is possible, though i'm only briefly aware of how Modbus works and don't know EGD.
>
> ...
Don't think we have dealt with any. A brief google search doesn't show much other than th... Jonathan Cormier

HB 09:42 AM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: Communication EGD or ModBus/TCP Cores

Hi,
I'm a beginner with FPGA and embedded systems, now I'm creating a communication between some devices and the MitySOM1810 through EGD and ModBus/TCP communication protocols.
After this stage we are thinking about implementing th... Hector Bojorquez

07/12/2016

JC 09:02 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: SPI1 controller, access to FLASH and carrier board. NOT linux based.

Excellent glad you got it working. Jonathan Cormier

IS 12:16 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: SPI1 controller, access to FLASH and carrier board. NOT linux based.

Johnathan,
Joy Joy, Happy Happy.
Everything is working. There were three items altogether. First was the "open drain" on the chip select. The EE added a pull up resistor and that worked). We were able to finally capture the spi si... Ian St. John

07/11/2016

FW 05:06 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: L138 dsplink problem - schedule while atomic bug

I looked deeper into the error we were provoking on our bench; it turned out to be a c++ vector de-referencing error that was causing an invalid page fault. The error message posted above appears to be secondary fallout. I'm thinking tha... Fred Weiser

AD 09:41 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: 5CSX-H6-53B-RC with PCIe Hard IP (Root)

Hi Tom,
As the Root Port, the HPS will control the reset to the PCIe. This can be an HPS GPIO, loaned pin, or FPGA I/O. A bank 8A pin is acceptable.
- Adam Adam Dziedzic

TC 09:02 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: 5CSX-H6-53B-RC with PCIe Hard IP (Root)

After a bit of rearranging, I've gained the use 179 (B8A_RX_T1_N/CLK7n) for the PERSTn. I believe that should work fine.
Thanks,
Tom. Thomas Carpenter

TC 08:37 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: 5CSX-H6-53B-RC with PCIe Hard IP (Root)

Hi Adam,
Thanks, I hadn't realised that restriction was just on CvP. As we don't need that, you say that any IO can be used.
Would HPS_GPIO44 (pin244 on the MitySOM) be usable if I set up HPS loaning for that pin so that the FPGA c... Thomas Carpenter

AD 08:11 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: 5CSX-H6-53B-RC with PCIe Hard IP (Root)

Hi Thomas,
The Cyclone V has a mode where it can be configured using CvP (Config via Protocol) - this configures the FPGA over the PCI Express bus interface. To use this mode, the PERSTN has only one option for the pin location. For... Adam Dziedzic

07/09/2016

TC 10:22 PM MitySOM-5CSX Altera Cyclone V FPGA Development: 5CSX-H6-53B-RC with PCIe Hard IP (Root)

Hi,
We are considering one of the MitySOM boards for use in one of the projects we are working on. I'm currently going over the pin mappings to make sure that we have enough pins.
I was reading through the design guide for the boar... Thomas Carpenter

JC 06:24 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: SPI1 controller, access to FLASH and carrier board. NOT linux based.

Ian St. John wrote:
> Can you confirm that the signal marked as 'reserved' just beside the SPI1_CSC1 is the SPI1_CSC0 and would that show the chip select operation from reading the flash? It seems a good inference but it is speculative ... Jonathan Cormier

IS 05:56 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: SPI1 controller, access to FLASH and carrier board. NOT linux based.

Hmm. I asked the EE about the diagram and he was interested in the fact that there was a pull up on the CS line. Apparently, none of our documents state that the SPI1_SCS[1] is "open drain".
We have
"am1808 tech ref (spruh82a)".pdf... Ian St. John

IS 12:40 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: SPI1 controller, access to FLASH and carrier board. NOT linux based.

The eeprom is on the i2c0 bus. I'm assuming you are talking about the SPI Nor flash which is on SPI1_CS0.+
Oops. Sorry, I said eeprom when I meant the 8MB flash. The JEDEC result is from FLASH, so ok. I modified the code to do the ... Ian St. John

MW 01:23 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: L138 dsplink problem - schedule while atomic bug

Hi Fred,
Syslink is newer than DSPlink, though in the context of the L138 it's very similar code (syslink evolved from DSPlink).
I am curious about the "sudden" appearance of the error following a power cycle on your fielded unit. ... Michael Williamson

FW 12:11 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: L138 dsplink problem - schedule while atomic bug

The error collected above was on the bench after making some minor software changes seemingly unrelated with the code that accesses dsp-link; the one below was just found in the field. The field device was in operation for 2 months with ... Fred Weiser

FW 11:23 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: L138 dsplink problem - schedule while atomic bug

I found the following on the TI site; looks like they struggled with this issue with sys-link... I'm not sure how sys-link is related to dsp-link (newer, older, ?)...
[[https://e2e.ti.com/support/embedded/tirtos/f/355/t/385081]] Fred Weiser

07/08/2016

FW 11:55 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: L138 dsplink problem - schedule while atomic bug

I think there may be a bug in the dsplink kernel code that causes the scheduler to run after a call to spinlock. "remove_wait_queue" seems to be in atomic code, and anything that can cause a call to the scheduler is not allowed after a s... Fred Weiser

JC 09:33 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: SPI1 controller, access to FLASH and carrier board. NOT linux based.

Ian St. John wrote:
> I am building and programming a custom board without Linux. Basic embedded drivers running from SPI1,CS0 (8MB NOR Flash).
> ...
The eeprom is on the i2c0 bus. I'm assuming you are talking about the SPI Nor flash... Jonathan Cormier

07/07/2016

DV 11:26 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: /sys/class/fpga-bridge directory is empty

Thank you for letting us know about this, it was a bug that was caused by some updates to the ethernet driver, which in turn caused some changes in the dtsi. I've pushed the fix to our git repo, it converts how the reset manager was inte... Daniel Vincelette

07/05/2016

IS 10:18 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: SPI1 controller, access to FLASH and carrier board. NOT linux based.

I am building and programming a custom board without Linux. Basic embedded drivers running from SPI1,CS0 (8MB NOR Flash).
CCS version 6.1.3, compiler TI 15.15.1 LTS, custom carrier board with 1808-FX-225-RC (MityARM 1808) SOM.
I can ... Ian St. John

06/30/2016

AB 11:08 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Why do I get a "CALIBRATION FAILED" error during boot?

Malcolm,
Thanks for catching the typo, it's been updated.
With the CSEL "properly" set and the module still not operating as expected it does still appear that an RMA will still need to be done for us to dig into the issue further.... Alexander Block

MH 03:49 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Why do I get a "CALIBRATION FAILED" error during boot?

Alex,
Thank you for the reply.
I've checked the "gotchas" wiki page and the CSEL setting was the only thing not correct (and now corrected).
A correction for the Wiki is to change "page 469" to "page 459" three lines up from th... Malcolm Hartnell

MC 09:31 AM MitySOM-5CSX Altera Cyclone V Software Development: /sys/class/fpga-bridge directory is empty

I downloaded the latest kernel sources from the critical link repo, rebuilt the kernel and .dtb files, and loaded them on the sdcard. Everything works fine except I lost the fpga2hps, hps2fpga, and lwhps2fpga folders under the /sys/clas... Mike Cherny

06/29/2016

AB 10:01 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Why do I get a "CALIBRATION FAILED" error during boot?

Malcolm,
Dan and Adam brought this issue to my attention and I will followup concerning the RMA replacement via e-mail.
Please note that the current Development Kit Hardware Quickstart Guide (https://support.criticallink.com/redmin... Alexander Block

MH 05:55 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Why do I get a "CALIBRATION FAILED" error during boot?

I've tried both suggestions but the result is the same, I get the "CALIBRATION FAILED" message on my first board and the second board works.
Can I send the SoM back for a replacement?
Thanks,
Malcolm Malcolm Hartnell

06/28/2016

MH 11:56 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Why do I get a "CALIBRATION FAILED" error during boot?

Dan,
I've downloaded the file you provided the link for but first ...
Adam,
I presently have CSEL[0-1] set to logic high as per the switch settings of the Critical Link dev board as it was supplied. I now have my own base board ... Malcolm Hartnell

AD 11:39 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Why do I get a "CALIBRATION FAILED" error during boot?

There is a CV errata that can cause such a failure. Please check that the CSEL[0-1] pins are set to "00" to avoid a potential HPS PLL issue.
!MSEL-CSEL-BSEL.png!
Thanks,
Adam Adam Dziedzic

DV 11:13 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Why do I get a "CALIBRATION FAILED" error during boot?

Hello Malcolm,
I know you said that your current SD card works for one of your SOMs but would you mind trying our prebuilt 5CSX-H6-4YA SD card image just to double check that the SOM that fails RAM calibration still acts the same? It ... Daniel Vincelette

MH 11:00 AM MitySOM-5CSX Altera Cyclone V Software Development: Why do I get a "CALIBRATION FAILED" error during boot?

I have been using the same module for the last two weeks and today it has started giving the "CALIBRATION FAILED" error message as listed on the Wiki's ARM Software FAQs page. Malcolm Hartnell

06/24/2016

DV 01:10 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Building BSP for 5cse

Hi Sam,
I've been able to recreate what you're seeing. It looks like the devicetree generated through yocto is named socfpga_mitysom5cse_devkit.dtb and what uboot is looking for on the SD image that ships with the 5CSE devkit is socfp... Daniel Vincelette

SS 06:41 AM MitySOM-5CSX Altera Cyclone V PCB Development: RE: Development Kit 2.5V VIO, change to 3.0 or 3.3

Thank you Alex, that's exactly what I wanted to know. I understand your point about the warranty, and proceeding carefully.
Best,
Steve Stephen Snyder