Activity
From 08/14/2026 to 09/12/2026
08/20/2026
- Hello Sir/Madam,
I'm trying to create Programming File Generator for our own project based on your example design. Your eaxample design uses Makefile that build, compile and generate programming Files. We have our own scripts to build... - Subject: PCIe Root Port bring-up on MitySOM-A5E (A5ED-B64-144-SRC-X) — hard system hang, likely missing GTS reset sequencer for right-side bank
Setup:
Board: MitySOM-A5E, part A5ED-B64-144-SRC-X, mitysom-a5e-ref-base project, pro_2...
08/14/2026
- MF 07:12 PM PCB Development: RE: MitySOM Standard Carrier Board FMC pin assignment typo
- Hi Max,
I reviewed your pinout and it looks correct to me.
One thing to mention is that I have posted our FMC example design and Wiki page here: [[A5E-FMC-Example]]. You obviously don't need to use this example design as you presum... - MK 05:33 PM PCB Development: RE: MitySOM Standard Carrier Board FMC pin assignment typo
- Hello Mike, thank you so much for your help!!!
I'va attached my pin assignment table with fixes. Can you please take a look and see if exerything is correct. Meanwhile, I'll try to compile with these modifications.
Thanks,
Max - MF 05:20 PM PCB Development: RE: MitySOM Standard Carrier Board FMC pin assignment typo
- Hi Max,
You are correct, it is a typo in the FPGA Pin column and not a board issue. Both nets route correctly on the carrier and on the SoM.
Your D12 row is the good one:
* D12 (LA05_N), HVIO route: SoM pin J1-C12, HVIO_6A_12, F... - MK 04:29 PM PCB Development: RE: MitySOM Standard Carrier Board FMC pin assignment typo
- In addition to previous message, pin H8 also doesn't seems to be right connection (VR31)
- Hello dear Sir/Madam,
I found some small typo in document: MitySOM-A5E-Standard-Development-Kit-Datasheet.pdf (inside document: 60-000098 Rev 1A):
- in table Table 17: J3 Connector Pin Assignments, pin C10 assigned to FPGA Pin: BR22
...