Mity CPU Platforms » MitySBC-Agilex5

Eleonora,

Our Makefile is currently configured to support Linux. So installing Quartus inside of WSL or a Linux VM would make following our Wiki instructions easier.

That said, you could try the following to convert your JIC then circle back to compiling the bootloader yourself:

You should be able to convert the SOF to JIC using the pre-compiled bootloader configuration data I have attached to this post. You should be able to open the "Embedded Command Shell" from the Quartus install, or navigate to where quartus_pgm.exe is installed in the Quartus installation path with a regular command prompt terminal and run the following:

quartus_pfg.exe -c -o hps_path=/path/to/u-boot-spl.ihex -o hps=on -o device=MT25QU256 -o mode=ASX4 -o flash_loader=A5ED065BB32AE6SR0 /path/to/SOF_FILE /path/to/OUTPUT_JIC

This will combine the SOF with the bootloader data to make the JIC file.

To do this manually, you'd have to look in our Makefile and see how the ATF and Bootloader source is checked out and compiled. You stated that you installed the prerequisites into your WSL install, so I assume you installed the GCC toolchain. Therefore, you should have what you need to compile this. It would look something like the following:

# Compile the ATF
git clone -b QPDS25.3_REL_GSRD_PR https://github.com/altera-opensource/arm-trusted-firmware 
sed -i 's/PLAT_UART0_BASE/PLAT_UART1_BASE/g' arm-trusted-firmware/plat/intel/soc/common/include/platform_def.h
CROSS_COMPILE=aarch64-none-linux-gnu- make -j 4 -C arm-trusted-firmware  PLAT=agilex5 bl31

# Clone bootloader source
git clone -b socfpga_v2025.07 https://git.criticallink.com/git/u-boot-socfpga.git

# Symlink the ATF binary to bootloader source
ln -sfr arm-trusted-firmware/build/agilex5/release/bl31.bin u-boot-socfpga/

# Compile bootloader
CROSS_COMPILE=aarch64-none-linux-gnu- ARCH=arm64 make -j 4 -C u-boot-socfpga socfpga_mitysbc_a5e_defconfig
CROSS_COMPILE=aarch64-none-linux-gnu- ARCH=arm64 make -j 4 -C u-boot-socfpga
aarch64-none-linux-gnu-objcopy  -I binary -O ihex --change-addresses 0x0 u-boot-socfpga/spl/u-boot-spl-dtb.bin u-boot-socfpga/spl/u-boot-spl.ihex

# This makes the u-boot-socfpga/spl/u-boot-spl.ihex I have attached to this post
# At this point you would run the quartus_pfg command I listed above to combined the u-boot-spl.ihex with the SOF to make the JIC

Once you have the JIC you can program it onto the baseboard. However, you still need to place the a5e.core.rbf into /lib/firmware/a5e.core.rbf of the SD card. How the boot flow for our base project is setup is that the HPS is initialized first and the bootloader is responsible for loading the FPGA (a5e.core.rbf) image during boot.