Mity CPU Platforms » MitySBC-Agilex5

11/07/2025

04:38 PM FPGA Development: RE: MitySBC A5E

Thank you for the information. I am guessing the pre-installed FPGA does not enable FMC_EN_3V3.
I will start with o... Sung Lim

04:24 PM FPGA Development: RE: MitySBC A5E

Hi Sung,
From the datasheet (page 14):
"All power to the FMC connector is gated by FMC_EN_3V3 which is tied to ... Michael Williamson

03:06 PM FPGA Development: MitySBC A5E

Two questions:
1. On the prototype board, FMC +12V and +3.3V do not appear to be driven. Is there a strapping optio... Sung Lim

10/17/2025

07:30 PM FPGA Development: RE: MitySOM-A5E PCIe HIP configuration qudstion

Yes, agreed. It would be a good upgrade path without jumping the SOC family. Sung Lim

07:05 PM FPGA Development: RE: MitySOM-A5E PCIe HIP configuration qudstion

Hi Sung,
With a higher speedgrade option, you can get PCIe x4 gen 4 if bandwidth is a concern and the other end po... Michael Williamson

06:39 PM FPGA Development: RE: MitySOM-A5E PCIe HIP configuration qudstion

Thank you again for the prompt response. PCIe x4 gen 3 (4GB/s bus limit) should be sufficient for this generation of... Sung Lim

05:11 PM FPGA Development: RE: MitySOM-A5E PCIe HIP configuration qudstion

Sung,
All of our current Agilex 5 platforms are E-Series, Device Group B devices. Therefore, they only support up ... Mike Fiorenza

04:58 PM FPGA Development: MitySOM-A5E PCIe HIP configuration qudstion

In the MitySOM-A5E datasheet, "up to six x4 PCIe 4.0 hard IP blocks" are supported.
Can some of the PCIe be configur... Sung Lim