Activity
From 10/13/2025 to 11/11/2025
11/07/2025
- SL 04:38 PM FPGA Development: RE: MitySBC A5E
- Thank you for the information. I am guessing the pre-installed FPGA does not enable FMC_EN_3V3.
I will start with one of the available reference projects.
Best regards, Sung Lim - MW 04:24 PM FPGA Development: RE: MitySBC A5E
- Hi Sung,
From the datasheet (page 14):
"All power to the FMC connector is gated by FMC_EN_3V3 which is tied to pin CG134 of the FPGA."
This will enable the +12V FMC power supply and the +3.3V FMC power Supply. VADJ should alrea... - Two questions:
1. On the prototype board, FMC +12V and +3.3V do not appear to be driven. Is there a strapping option to supply the two voltages from the SBC?
2. Would it be possible to obtain the Quartus pro project for the base FPGA?...
10/17/2025
- SL 07:30 PM FPGA Development: RE: MitySOM-A5E PCIe HIP configuration qudstion
- Yes, agreed. It would be a good upgrade path without jumping the SOC family.
- MW 07:05 PM FPGA Development: RE: MitySOM-A5E PCIe HIP configuration qudstion
- Hi Sung,
With a higher speedgrade option, you can get PCIe x4 gen 4 if bandwidth is a concern and the other end point / root port supports it.
With regards,
Mike - SL 06:39 PM FPGA Development: RE: MitySOM-A5E PCIe HIP configuration qudstion
- Thank you again for the prompt response. PCIe x4 gen 3 (4GB/s bus limit) should be sufficient for this generation of products.
- MF 05:11 PM FPGA Development: RE: MitySOM-A5E PCIe HIP configuration qudstion
- Sung,
All of our current Agilex 5 platforms are E-Series, Device Group B devices. Therefore, they only support up to PCIe x4 configurations (not x8). You need a D-series device to support x8.
- Mike - In the MitySOM-A5E datasheet, "up to six x4 PCIe 4.0 hard IP blocks" are supported.
Can some of the PCIe be configured as x8 (three x8 instead of six x4, for example)?