Programming the DevKit Silicon Labs PLL¶
The MitySOM-A5E development kit carrier card includes a si5338 4 channel (differential) Phase Lock Loop Chip.
The PLL chip is provided a (coherent) copy of the 25 MHz reference clock sourced by the SOM. This same clock is also fed back to the SOM on an HPS IO pin to support clocking the HPS and it's PLLs. The PLL chip is powered with 1.8V and uses 1.8V on the I2C control port.
The default PLL configuration for the revision 1 carrier board is as follows:
| PLL Ref Des | I2C1 Address | Clock Index | Frequency (MHz) | Standard | Connection | Notes |
|---|---|---|---|---|---|---|
| U10 | 0x70 | 0 | 156.25 | LVDS (AC) | FPGA REFCLK_GTSL1B_RX (BA66/BA69) | Intended for SFP+ Port |
| U10 | 0x70 | 1 | 150 | LVDS (AC) | FPGA REFCLK_GTSL1C_RX (AU66/AU69) | Intended for Display Port |
| U10 | 0x70 | 2 | 100 | LVDS (AC) | FPGA REFCLK_GTSL1C_CH1 (AR66/AR69) | Spare |
| U10 | 0x70 | 3 | 20 | LVDS (DC) | FPGA DIFF_IO_3A_T19 (P22/V22) | Intended for MIPI or LVDS |
The default PLL configuration for the revision 2 carrier board is as follows:
| PLL Ref Des | I2C1 Address | Clock Index | Frequency (MHz) | Standard | Connection | Notes |
|---|---|---|---|---|---|---|
| U10 | 0x70 | 0 | 150 | HCSL (AC) | FPGA REFCLK_GTSL1B_RX (BA66/BA69) | Intended for SFP+ Port |
| U10 | 0x70 | 1 | 156.25 | HCSL (AC) | FPGA REFCLK_GTSL1C_RX (AU66/AU69) | Intended for Display Port |
| U10 | 0x70 | 2 | 100 | HCSL (AC) | FPGA REFCLK_GTSL1C_CH1 (AR66/AR69) | Intended for USB 3.0 |
| U10 | 0x70 | 3 | 20 | LVDS (DC) | FPGA DIFF_IO_3A_T18 (K21/K24) | Intended for MIPI or LVDS |
The root filesystem includes a perl script developed by Intel in /usr/bin/si5338_cfg that may be used to program the SI5338 device from the HPS should an alternate clocking scheme be needed.
In addition, there is a fixed 100 MHz HCSL clock driver feeding FPGA REFCLK_GTSR4C_RX (AY17/AY19) in order to support the PCIe interface.
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