Where can I find the schematic for MitySBC_Agilex5
Go to top
Added by Eleonora Haralanova about 5 hours ago
Hello,
I'm trying to instantiate 3 PCIe Gen3 x4 lanes IPs in the FPGA but can't figure out which pins are available to use. From the datasheet - the M2 connector is one, then the FMC has another 4 lanes, but I don't see where to put the third IP because the display port uses another 4 lanes, but it shows only the TX side connected. Is there a schematic that I can use?
The 3 PCIe x4 lanes is the bare minimum that I need as far as transceivers go. I would prefer to be able to get 2 of the PCIe as x8 and one x4 lanes. I would be grateful for any information.
Thank you,
Eleonora