Where can I find the schematic for MitySBC_Agilex5
Added by Eleonora Haralanova about 10 hours ago
Hello,
I'm trying to instantiate 3 PCIe Gen3 x4 lanes IPs in the FPGA but can't figure out which pins are available to use. From the datasheet - the M2 connector is one, then the FMC has another 4 lanes, but I don't see where to put the third IP because the display port uses another 4 lanes, but it shows only the TX side connected. Is there a schematic that I can use?
The 3 PCIe x4 lanes is the bare minimum that I need as far as transceivers go. I would prefer to be able to get 2 of the PCIe as x8 and one x4 lanes. I would be grateful for any information.
Thank you,
Eleonora
Replies (1)
RE: Where can I find the schematic for MitySBC_Agilex5 - Added by Michael Williamson about 5 hours ago
Hello Eleonora,
To confirm, are you using the MitySBC hardware? If so then the three possible banks for PCIe x4 would be:
Bank GTSL1B (M.2 Connector)
Bank GTSR4B (FMC DP0->DP3)
Bank GTSR4A (FMC DP5->DP7 .... reversed connections to CH4->CH0)
The Agilex-5 E series does not support bonding past x4 lanes, so I don't believe x8 is possible.
If you are working with a sales rep, please let him know you need schematics and we can provide them.
With regards,
Mike
