Where can I find the schematic for MitySBC_Agilex5
Added by Eleonora Haralanova 27 days ago
Hello,
I'm trying to instantiate 3 PCIe Gen3 x4 lanes IPs in the FPGA but can't figure out which pins are available to use. From the datasheet - the M2 connector is one, then the FMC has another 4 lanes, but I don't see where to put the third IP because the display port uses another 4 lanes, but it shows only the TX side connected. Is there a schematic that I can use?
The 3 PCIe x4 lanes is the bare minimum that I need as far as transceivers go. I would prefer to be able to get 2 of the PCIe as x8 and one x4 lanes. I would be grateful for any information.
Thank you,
Eleonora
Replies (5)
RE: Where can I find the schematic for MitySBC_Agilex5 - Added by Michael Williamson 27 days ago
Hello Eleonora,
To confirm, are you using the MitySBC hardware? If so then the three possible banks for PCIe x4 would be:
Bank GTSL1B (M.2 Connector)
Bank GTSR4B (FMC DP0->DP3)
Bank GTSR4A (FMC DP5->DP7 .... reversed connections to CH4->CH0)
The Agilex-5 E series does not support bonding past x4 lanes, so I don't believe x8 is possible.
If you are working with a sales rep, please let him know you need schematics and we can provide them.
With regards,
Mike
RE: Where can I find the schematic for MitySBC_Agilex5 - Added by Eleonora Haralanova 26 days ago
Thank you, Mike.
I was asking about the schematic, because I don't have information about all the pins that are connected on the PFGA. We are working with Arrow, so I'll ask them for schematic, but can you answer few more questions about the clocks.
IF I utilize GTSR4A and GTSR4B for PCIe Gen3 x4, I need 2 pairs of clock pins in those banks for ref_clk. Those are not the once that are connected to the Si5883 devices.
In the reference designs, I see
i_fmc_gbt_clk0_p, PIN_AV16 bank 4B
i_fmc_gbt_clk1_p, PIN_BB16 bank 4A
Since these clocks are not used, only positive pins are shown and I don't know if the negative pins are connected. Nor does it specify the clock frequencies.
Also, for the bank GTSL1B, do I use as reference
i_mge_ref_clk(n) PIN_AT115 1C
i_mge_ref_clk PIN_AT120 1C
It's not enabled output from the Si device at the moment, but can be reprogrammed.
OR do I actually need
PIN_AV115 1B
PIN_AV120 1B
Eleonora
RE: Where can I find the schematic for MitySBC_Agilex5 - Added by Michael Williamson 26 days ago
Hi Eleonora,
Are you trying to run EP or RP?
The GBTCLK0_M2C_P/N on FMC D4/D5 is run to REFCLK_GSTR4B_CH1p/n (AV16 AV21) of the FPGA.
The GBTCLK1_M2C_P/N on FMC B20/B21 is run to REFCLK_GSTR4A_CH1p/n (BB16 BB21) of the FPGA.
These would work for EP.
If you need RP, you might have to forward a 100 MHz clock up to the FMC clock and then somehow double it and route it back down to the inputs.
Are you designing your own FMC card or do you have a specific one in mind?
Thanks,
Mike
RE: Where can I find the schematic for MitySBC_Agilex5 - Added by Michael Williamson 5 days ago
Hi Eleonora,
I was advised that you are working with our MitySOM-A5E product vs. our MitySBC-A5E product. I apologize, I thought you were using our MitySBC-A5E product as this forum is for that product line.
If this is the case, please check this wiki area (and use the forums are there for any additional questions):
https://support.criticallink.com/redmine/projects/mitysom_a5/wiki
There are links on that page to get the schematics for the carrier card that includes the clocking PLL chip and all the connections.
We don't typically provide schematics for the SOM and our SBC schematics, but it's not clear you need them to sort out the clocking question you have.
There is a link on that page to get information about programming the PLLs and changing them.
Hopefully this helps. If you are indeed using the MitySBC, I will work to get you the needed schematic information.
With regards,
Mike
RE: Where can I find the schematic for MitySBC_Agilex5 - Added by Eleonora Haralanova 4 days ago
Thank you Mike.
We currently have SBC and SOM Dev kit. We were told that they are equivalent from FPGA connections point of view, but I found out that's not completely correct.
I need the schematic to figure out which FPGA pins and how are connected to the FMC in case I have to loop back a clock to the transceivers so I can have PCIe RootPort, as per earlier suggestion.
In the future, I'll switch to the correct forum.
Eleonora
---------------------------------------------------------
Name : Eleonora Haralanova | FPGA Design Engineer
Company: Wideband Systems, Inc.
Address : 11900 Bournefield Way - Suite 120
Silver Spring, MD 20904
Office : +1 301-588-8840 x111
Mobile : +1-xxx-xxx-xxxx
Website : wideband-sys.com
[Logo, company name Description automatically generated]
The Delta Family of Companies
Delta Digital Video Video Compression Products
GDP Space Systems - Aerospace Telemetry Systems
Acroamatics - Telemetry Processing and Display Systems
Ampex Data Systems Corp - Airborne Solid State Recorders
Wideband Systems - Advanced Recording Solutions
-------------------------------------------------------------
